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Jane Street has explained that its August ASIC reverse-engineering puzzle contained a hardware checker for an 11-by-11 Star Battle puzzle. The company reported about 400 submissions from more than 30 countries and described several methods participants used to recover and test the circuit.
Jane Street has revealed that an ASIC layout it released as a reverse-engineering puzzle was a hardware checker for an 11-by-11 Star Battle board. The firm said it received about 400 submissions from more than 30 countries, making the results a look at both the chip’s design and the varied methods solvers used to uncover its function.
The puzzle supplied the chip’s final GDS layout, a physical description of its circuit, but withheld the netlist and internal signal names. Participants had to reconstruct the logic and work out what inputs produced the chip’s success output. Jane Street said the design checks a board over 121 input cycles, with each input indicating whether a star is placed in one square.
As described in the results post, the circuit checks that each row, column and colored region contains exactly two stars, and that no pair of stars touches, including diagonally. Separate counters track rows, columns, regions and total stars, while a delay line checks neighboring squares. The checks combine into a success signal.
The output logic stores strings in ROM and uses a small linear-feedback shift register to obfuscate the solution text. On success, the circuit deobfuscates and emits “TWO STARS.” Jane Street said most invalid boards produce “TRY AGAIN,” while some inputs trigger Easter egg outputs. The company identifies the design as built with the SKY130 open-source standard cell library and LibreLane toolchain.
How Solvers Reconstructed the Chip
The results show how a physical circuit layout can be treated as a software and logic problem even when its netlist and signal labels are absent. Solvers first had to extract or infer the gates, then simulate their behavior, and finally test candidate boards against the puzzle’s constraints. That made the task more than simply guessing the intended Star Battle solution: a correct result depended on understanding how the chip processed its inputs.
Jane Street described approaches ranging from extracting a gate-level netlist with existing tools to writing custom extraction pipelines and circuit evaluators. Some participants worked backward from the success signal; others changed inputs and watched which registers responded. These methods matter because they exposed different ways to analyze the same design—and, as one reported modeling error illustrates, why matching a supplied test trace alone may not prove a simulator is accurate.
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From Layout to Star Battle
Jane Street’s original puzzle, published in August, provided the final GDS layout and asked readers to determine what the small chip did. The layout retained standard-cell names, which the company said made extraction easier with tools such as Magic and KLayout. Some entrants went further and wrote their own tools to recover circuit connectivity from the physical shapes.
The company reported submissions from high school students, researchers, working engineers and retirees, with entries coming from more than 30 countries. It said most solvers used KLayout, Yosys and Z3 alongside custom programs. The writeup highlights examples involving C++, Python and other languages, as well as simulations built from existing SKY130 models or written from scratch.
One account described in the post illustrates a verification pitfall: a Python model reproduced the supplied waveform but mishandled tie-high cells, which should provide a constant one. That error disabled the adjacency check in the model. Its author caught the problem by comparing results against a separate Icarus Verilog simulation using additional inputs, according to Jane Street’s summary.
“The chip is a hardware checker for an 11×11 Star Battle puzzle.”
— Jane Street
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Limits of the Published Results
The source reports an approximate submission count and broad participant locations, but does not provide a complete breakdown of entries, solve rates or the number of independently correct solutions. It also does not state the year in which the August puzzle or results post appeared. The examples in the article are selected writeups, not a full account of every method used.
Jane Street explains the intended circuit behavior, but the supplied material does not include an independent audit of the design or the submissions. The described simulator bug also shows that a model can match a provided waveform while still mishandling other inputs. The results post does not quantify how many participants encountered similar issues or how many submissions triggered Easter eggs.
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Further Writeups and Circuit Details
Jane Street’s results post points readers to selected participant writeups that document netlist extraction, simulation and logic analysis in greater depth. Those accounts provide the next step for readers who want to reproduce a solution or compare approaches. The source material does not announce another puzzle, a deadline or a planned follow-up from the company, so no further release is confirmed.
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Key Questions
What did the ASIC puzzle chip do?
Jane Street says it checked an 11-by-11 Star Battle board for the required star counts in each row, column and colored region, while rejecting stars that touch, including diagonally.
How many submissions did Jane Street receive?
The company reported about 400 submissions from more than 30 countries. It did not provide a full count of correct solutions.
What does the chip output for a correct board?
According to Jane Street, a successful input causes the output logic to reveal the string “TWO STARS.” Most incorrect boards produce “TRY AGAIN,” with some triggering Easter egg outputs.
How did participants analyze the layout?
Approaches included extracting a gate-level netlist with existing tools, writing custom extraction software, simulating the circuit, tracing logic backward from the success signal and testing how registers responded to changed inputs.
Is another ASIC puzzle confirmed?
The results material provided here does not announce another puzzle or give a date for one. Any future challenge remains unconfirmed.
Source: hn
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